1 Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof including STI structures, and in particular, it is intended for a semiconductor memory including a transistor structure and a capacitor structure in a memory cell region.
2 Description of the Related Art
In a semiconductor memory device having memory cells taking a constitution storing a data into a capacitor structure, various device configurations are thought out whose objects are to reduce a memory cell area and to improve a degree of integration. In particular, when so-called an STI (Shallow Trench Isolation) structure is used as an element isolation structure, a capacitor structure (isolation/consolidation type capacitor structure) is proposed in which even sidewall portions of isolation trenches are used as component parts of a capacitor, and it is electrically isolated from adjacent memory cells by a buried insulating film at a bottom portion of the isolation trench (refer to Patent Document 1 and so on).
[Patent Document 1] Japanese Patent Application Laid-open No. 2003-92364
Recently, further improvement in a degree of integration is required in a semiconductor memory, and a configuration described in the Patent Document 1 and so on becomes inadequate to comply the request.
A miniaturization of an isolation trench width in the STI structure becomes necessary to realize further improvement in the degree of integration in the semiconductor memory. Meanwhile, a depth of the isolation trench is required to be shallow in reverse from a restriction of a filling property of an insulator into the isolation trench. It is therefore required to enhance a substrate concentration as much as possible by forming so-called a channel stop region by doping an impurity under the insulator filling the isolation trench to secure an enough element isolation ability.
In an isolation/consolidation type capacitor structure, the insulator in the isolation trench corresponding to a formation portion of the corresponding capacitor structure among the isolation trenches is etched to expose an upper portion of a sidewall surface of the isolation trench. It is therefore inevitable that, for example, as shown in FIG. 1, an insulator 112 of an STI structure 102 existing at the formation portion of the corresponding capacitor structure becomes thinner than an insulator 111 of an STI structure 101 existing at a portion other than the formation portion. Consequently, after the insulator 112 is etched to form STI structure 102, the impurity for a channel stop is simultaneously ion implanted into lower portions of the STI structures 101, 102 while the lower portion of the STI structure 101 is used as a reference, and then, a channel stop region 103 which is deeper at a portion under the STI structure 102 than at another portion under the STI structure 101 is formed (shown by inside of a circle in FIG. 1). The channel stop region 103 is too deep under the STI structure 102, and therefore, there is a problem that the substrate concentration immediately under the STI structure 102 becomes thin to cause a deterioration of the element isolation ability.
It can be said that a simultaneous forming of the channel stop region at the lower portions of the STI structures 101, 102 by one time ion implantation is inevitable to avoid an increase of process steps and a complication of a manufacturing process. On the assumption of the above, it is necessary to form the channel stop region at a stage that film thicknesses of the insulating films 111, 112 are the same (before a surface layer of the insulating film 112 is etched), to form the channel stop region under the STI structures 101, 102 at equivalent positions.
In detail, at first, the impurity for the channel stop is simultaneously ion implanted into the lower portions of the STI structures 101, 102 before the surface layer of the insulating film 112 is etched, as shown in FIG. 2A. At this time, the channel stop region 103 is formed in an equivalent depth at the lower portions of the STI structures 101, 102.
Subsequently, a resist mask 113 opening the STI structure 102 is formed as shown in FIG. 2B, and a part of the insulator 112 inside of the STI structure 102 is etch removed by using this resist mask 113. Here, it is required to surely take an alignment margin when the resist mask 113 is formed, and therefore, an opening 113a of the resist mask 113 is formed larger than a width size of the isolation trench of the STI structure 102 by a lithography. A dry etching is performed in a state the resist mask 113 is formed as stated above, and therefore, a part of a substrate surface 114 exposing from the opening 113a of the resist mask 113 is also subjected to the etching when the insulator 112 is etched, and receives an etching damage. Namely, various molecules included in an etching gas go inside of the substrate from the part of the substrate surface 114, and the molecules become enhanced oxidation factors in a subsequent forming process of an oxide film (or an oxynitride film) (forming process of a capacitor insulating film). A substantial film thickness of the capacitor insulating film increases by an enhanced oxidation originated in the above, then a desired and designed value of capacity cannot be obtained because a capacity value becomes a small value, and a problem occurs in which a dispersion of the capacity becomes large.